Simulation has long been used in the design and manufacture of microelectronic circuits and systems. Present day Ultra-Large Scale Integration (ULSI) devices may include up to hundreds of thousands, millions or more passive electric components and/or active electronic components in a microelectronic device, such as an integrated circuit chip, which are interconnected on the chip to perform a particular function. The large capital investment that generally is needed to fabricate microelectronic devices and the potential difficulty in reworking microelectronic devices which do not operate as planned, may increase the need to simulate circuit performance before manufacture.
Accordingly, many circuit simulators have been developed and marketed. Circuit simulators are typically software based, and are designed to accept a description of the circuit which defines the circuit topology and element values. Each element in the circuit is typically specified by an element line containing the element name, connected nodes, and electrical parameter values. Simulators typically simulate circuits which contain passive (electric) components such as resistors, capacitors, inductors, mutual inductors, interconnects, voltage sources and current sources, and active (electronic) components such as diodes, bipolar junction transistors (BJT), junction field effect transistors (JFET) and metal oxide semiconductor field effect transistors (MOSFET). The simulator can typically be configured to generate a resistive-inductive-capacitive (RLC) equivalent circuit of the microelectronic device and to perform DC analysis, AC small signal analysis and/or transient analysis.
As the feature size of integrated circuits continues to shrink, and operating speeds increase, the characterization of the parasitic effects among the passive and active components may become difficult. For example, technology improvements for integrated circuits can continually decrease minimal feature sizes such that the task of modeling short-range parasitic interconnect couplings may become increasingly complex. The same technology improvements can facilitate larger integrated circuits/systems that are realized via component-based design methods to cope with design complexity and time-to-market constraints. The parasitics and the component based methods may make it desirable to model couplings between large portions of an integrated circuit chip for which the individual interconnect-to-interconnect couplings may be largely insignificant but the collective effect of all couplings may be important. Hierarchical models for interconnect parasitics therefore may become desirable for such systems.
At the lowest levels of modeling detail, hierarchical approaches have been used for interconnect parasitic extraction via a fast multipole method and a hierarchical refinement method. See, Greengard, The Rapid Evaluation of Potential Fields in Particle Systems, The MIT Press, Cambridge, Mass., 1987, and Nabors et al., FastCap: A Multipole Accelerated 3-D Capacitance Extraction Program, IEEE Trans. CAD, Vol. 10, No. 11, November 1991, pp. 1447–1459, respectively. These strategies can reduce the extraction complexity, usually to order linear in the number of source objects in the system. Conceptually this complexity reduction is made possible by representing the collective couplings/interactions between groups of conductors. Unfortunately, this hierarchy may be destroyed when the RLC equivalent circuit models are created for simulation.
More specifically, to map the extraction models to equivalent circuits, the far away coupling terms are typically discarded, or treated as couplings to ground. However, with the increasing dominance of coupling capacitance, and the emergence of on-chip inductance, modeling and design management of electromagnetic interactions between interconnects may become increasingly important. Even though the individual couplings between interconnect segments in adjacent components can be inconsequential, the composite couplings between the collective interconnects in each component can have a significant impact on performance. In addition, truncation of far field couplings to localize parasitic couplings can cause instabilities in the localized models. See, for example, Beattie et al., IC Analyses Including Extracted Inductance Models, 36th Design Automation Conference (DAC), June 1999.
In some cases design rules and rigid design practices can be enforced so that simpler models and analyses can be applied for final design verification. However, even in such cases, some understanding of the exact solution and the actual electromagnetic couplings, may be desired to validate the design rules.